; >1MExspsrc
; ARCHIMEDES TEST SOFTWARE
; Version 1.10     4-9-1987
; DRAM Test Programme
; Modified to produce 1Mbyte DRAM module test for avon  6th-April-1989
; Set memory locations top and bottom
; NOTE  VDU21 USED AFTER KEY - not required anymore 
; Did not use GetEnv to find top could not be sure that if certain memory
; faults occur GetEnv would return highest address (2M-1) - might return 
; highest address it could find which could be 1.5M - top 0.5M faulty but 
; never tested
; SWI ValidateAddress used to provide friendly error message to production
; rather than system error trap (address exception etc.).
; ************************************************************************
; For dealer mod to press space bar to continue
; On error cannot find memory do not exit until space bar pressed
; Change name of file from Expmemsrc to 1mexspsrc
; Change location of header directory 

 GET $.UPGRADES.MEMORY.HDR.LISTOPTS     ; Load in definitions of swi etc.
 GET $.UPGRADES.MEMORY.HDR.MACROS       ; Directory hdr and files listopts,
                                        ; macros and system
 GET $.UPGRADES.MEMORY.HDR.SYSTEM       ; should also be on the disc


SCAN * &79              ;Scan the keyboard
SPACE * 98              ;Space bar
 LEADR &8000            ;Load address
 SWI OS_WriteS
 = 22,7                 ;Set screen mode 7
 MOV R0,#6
 SWI OS_WriteC
 MOV R0,#12
 SWI OS_WriteC
 SWI OS_WriteS
 = 10,10,133,"      1 Mbyte Dram Expansion Test",10,13,0
 SWI OS_WriteS
 = 133,"      ___________________________",10,13,0
;SWI OS_GetEnv            ;Find the top of memory
 LDR R0,MEM2           ;Check memory exists between these locations 
 LDR R1,MEM1           ;Give friendly error message
 SWI OS_ValidateAddress
 BCC STEST
 SWI OS_WriteS
 = 10,13,131,"Cannot find memory upgrade card",10,0
 SWI OS_WriteS
 = 10,13,131,"Memory test Failed",135,10,13,0
 BL PRESPACE                ; Press space before exiting
 MOV PC,R14
 SWI OS_Exit
STEST LDR R1,MEM1           ;Load top address of memory
 MOV R12,R1
 MOV R10,R12
; BL WORDHX
 SWI OS_WriteS
 = 10,13,134," Phase one: incrementing pattern",135,0
 MOV R7,#4
 MOV R8,#0
PHASE1 LDR R0,P1PTN
 LDR R1,P1INC
 BL ENDADR
PH1FILL STR R0,[R4],#4 ; Store r0 in memory inc. location by 4
 ADD R0,R0,R1          ;inc data pattern by &0F020501 why?
 TEQ R4,R12            ;is [r4]=to top address
 BNE PH1FILL
 SWI OS_WriteI+"."
 BL ENDADR             ; pick up start address
 LDR R0,P1PTN
PH1CHK LDR R2,[R4],#4
 TEQ R2,R0             ;is it correct
 BNE PH1FAIL
PH1CONT ADD R0,R0,R1   ; inc pattern
 TEQ R4,R12            ; test end of block
 BNE PH1CHK
 STR R0,P1PTN          ; whats this!
 SUBS R7,R7,#1
 BNE PHASE1
 TEQ R8,#0             ;any failures
 BNE PHASEDEAD
 SWI OS_WriteS
 = 10,13,134," Phase two: TRUE hierarchy",135,0
 MOV R0,#0
 MVN R1,#0
 MOV R2,#2
PHASE2 BL ENDADR
PHASE2A TST R4,R2
 STREQ R0,[R4],#4
 STRNE R1,[R4],#4
 CMP R4,R12
 BCC PHASE2A
 SWI OS_WriteI+"."
 BL ENDADR
PHASE2B TST R4,R2
 LDR R3,[R4],#4
 BNE PHASE2B1
PHASE2B2 CMP R0,R3
 BNE PH2FAIL
 B PH2CONT
PHASE2B1 CMP R1,R3
 BNE PH2FAIL
PH2CONT CMP R4,R12
 BCC PHASE2B
 CMP R2,R12
 ADDCC R2,R2,R2
 BCC PHASE2
 TEQ R8,#0
 BNE PHASEDEAD
 TEQ R1,#0
 BEQ PHASE4
 SWI OS_WriteS
 = 10,13,134," Phase three: FALSE hierarchy",135,0
 MVN R0,#0
 MOV R1,#0
 MOV R2,#2
 B PHASE2
PHASE4 TEQ R8,#0
 BNE PHASEDEAD
 SWI OS_WriteS
 = 10,13,134," Phase four: Cycling bits",135,0
 MOV R7,#1
PHASE4A BL ENDADR
 MOV R2,R7
PHASE4A1 STR R2,[R4],#4
 MOV R2,R2,ROR #31
 CMP R4,R12
 BCC PHASE4A1
 SWI OS_WriteI+"."
 BL ENDADR
 MOV R2,R7
PHASE4B1 LDR R1,[R4],#4
 CMP R1,R2
 BNE PH4FAIL
PH4CONT MOV R2,R2,ROR #31
 CMP R4,R12
 BCC PHASE4B1
 ADDS R7,R7,R7
 BCC PHASE4A
 TEQ R8,#0
 BNE PHASEDEAD
 SWI OS_WriteS
 = 10,13,10,13,130,"  PASSED  ",10,13,0
PRESPACE SWI OS_WriteS
 = 10,13,130," Press Space to continue ",10,13,0
KEY MOV R0,#SCAN                                  ;Scan kybd
 MOV R1, #SPACE                                   ;Key to be detected
 SWI OS_Byte                                      ;Read key pressed
 CMP R1,#SPACE                                    ;Was it space bar
 BNE KEY                                          ;if not try again
 MOV R0,#21                                       ;turn off o/p to screen
 SWI OS_WriteC                                    ;while loading next prog
 SWI OS_Exit                                      ;Goodbye
PHASEDEAD SWI OS_WriteS
 = 10,13,129,"  There were &",0
 MOV R10,R8
 BL WORDHX
 SWI OS_WriteS
 = 129, " failures in total",10,13,0
 SWI OS_WriteS
 = 10,13,129,"   TESTING ABORTED",10,13,0
FIN BAL FIN
PH1FAIL CMP R8,#10
 ADD R8,R8,#1
 BCS PH1CONT
 SWI OS_WriteS
 = 10,13,"  Phase 1 fail at &",0
 MOV R5,R0
 SUB R10,R4,#4
 BL WORDHX
 SWI OS_WriteS
 = " with &",0
 MOV R10,R2
 BL WORDHX
 SWI OS_WriteS
 = " instead of &",0
 MOV R10,R5
 BL WORDHX
 MOV R0,R5
 B PH1CONT
PH2FAIL CMP R8,#10
 ADD R8,R8,#1
 BCS PH2CONT
 SWI OS_WriteS
 = 10,13,"  Phase 2 fail at &",0
 SUB R10,R4,#4
 MOV R5,R0
 BL WORDHX
 SWI OS_WriteS
 = " with &",0
 MOV R10,R3
 BL WORDHX
 SWI OS_WriteS
 = " instead of &",0
 TST R4,R2
 MOVNE R10,R1
 MOVEQ R10,R5
 BL WORDHX
 MOV R0,R5
 B PH2CONT
PH4FAIL CMP R8,#10
 ADD R8,R8,#1
 BCS PH4CONT
 SWI OS_WriteS
 = 10,13,"  Phase 4 fail at &",0
 SUB R10,R4,#4
 BL WORDHX
 SWI OS_WriteS
 = " with &",0
 MOV R10,R1
 BL WORDHX
 SWI OS_WriteS
 = " instead of &",0
 MOV R10,R2
 BL WORDHX
 B PH4CONT
MEM1  & &19C000    ;Top of memory to be tested
MEM2  & &A8000     ;Bottom of block of memory   1M  ?+byte to x boundary
P1PTN & &86427531
P1INC & &0F020501
WORDSP SWI OS_WriteI+" "
;print R10 using R0,R6,r9
WORDHX MOV R6,#32-4
WORDLP MOV R0,R10,LSR R6
 AND R0,R0,#15
 CMP R0,#9
 ORRLS R0,R0,#"0"
 ADDHI R0,R0,#"A"-10
 SWI OS_WriteC
 SUBS R6,R6,#4
 BPL WORDLP
 MOV PC,R14
ENDADR; ADR R4,ZEEND ;  Almost the end address of this file
 LDR R4,MEM2 ;   bottom of memory block
 MOV PC,R14
ZEEND
 END
